High-speed general purpose registers used in a central processing unit (CPU) are built up from multi-port static random access memories (SRAM). The multi-port SRAMs have n data input and data output ports and n separate write and read address ports. They are thus able to perform n separate data transfers during a single machine cycle. Such registers are normally required to possess so-called write-through capability, i.e. the data which is written into one of the storage cells of the memory via a write port is required to be read out through one or more read ports during the same cycle. This procedure is described in a number of prior art documents, including U.S. Pat. No. 4,157,586, "Technique For Performing Partial Stores in Store-Thru Memory Configuration," issued June 1979 to Gannon et al. and assigned to IBM.
An example of the realization of one such multi-port register is shown in FIG. 1, which is based on the implementation described in co-pending EP Published Application EP-A-0 434 852 (having a counterpart U.S. patent application Ser. No. 07/889,259, filed May 1992, continuation of Ser. No. 07/601,839, filed 23 Oct. 1990, abandoned) assigned to IBM. The depicted multi-port register 10 has only one write port 30 which is connected to a data input line 20. Three read ports 50a, 50b and 50c are each connected to separate data output lines 60a, 60b and 60c, respectively. A decoder 70 decodes the read addresses AR1, AR2, AR3 (one for each read port) and write address AW for the single write port appearing on lines 100a-c and 80, respectively, and selects the indicated word lines within a cell array 40. The cell array 40 comprises a number of asymmetrical static latches with separate buffers for driving the respective read ports, to enhance write-through speeds. A clock signal (CE) is provided on line 90 to the cell decoder 70 and to the cell array 40.
FIG. 2 shows a timing diagram for the write-through procedure carried out in conjunction with the multi-port array of FIG. 1. The write-through procedure is clocked from a clock signal (CE) and is edge triggered. The clock signal (CE) is used to strobe valid input data (DI) appearing on data input line 20 through the write port 30 into the cell array 40. Before the clock signal (CE) rises, the data input (DI) signal on data input line 20 and address signals (AW, AR) must be valid. The address signals comprise the write address signal (AW) indicating the write port address at which the input data (DI) on data input line 20 is to be written, and the read address signals (AR; AR1, AR2, AR3) indicating the address from which output data (DO; DO1, DO2, DO3) is to be output on data out lines 60a-c through read ports 50a-c, respectively. The minimum required set up time for the address signals (AW, AR) is shown on FIG. 2 as Ts.
The register 10 starts the write-through cycle as soon as the clock signal (CE) goes positive. The clock signal (CE) must be held high for a minimum time Tce until valid output data (DO) appears on the data output lines 60a-c after access time Tac, the time between when the read addresses are valid and valid output data appears on the output ports. Note that both the data input (DI) and address signals (AR, AW) must stay valid for longer than time Tce. The extra time these signals remain valid is denoted Th, and is referenced to the negative clock edge of CE. Before the next write cycle begins, the clock signal (CE) goes low.
The problem with this prior art solution is that the access time Tac is large since it comprises the time needed to overwrite the latch of the SRAM cell, as well as the time needed to read the data out of the cell. That is, note that a single decoder is used for both the read and write addresses. Because the decoder must decode the write addresses at the start of the cycle, all of its inputs (including the read addresses) must be valid at the time CE rises.
A prior solution to reducing timing dependencies imposed by clocks was the use of non-clocked SRAMs, in which no clocking is used to gate the address signals. See the general discussion at Cols. 1-2 of U.S. Pat. No. 4,845,676, entitled "Non-Clocked Static Memory Cell," issued to Lohlein et al. and assigned to IBM. However, in such systems typically the read and write addresses were provided at the same time, which would not address the problem discussed above. Moreover, having no clocking at all raises the possibility of erroneous memory operations due to mistimings of the respective memory operations, particularly during the access cycle.
Thus, a need exists in the art to avoid the long read access times of conventional clocked SRAMs, without introducing sufficient timing uncertainties to produce erroneous operations.